The next-generation wireline and wireless systems promise wider bandwidth to enable a vast range of applications, including autonomous vehicles, virtual reality, and the internet of things.
Such high data rates mandate precise clock generation to meet the timing budget. At the same time, flexibility to support multiple standards and scalability to meet higher integration density introduces additional dimensions to the clocking challenge. This talk will discuss recent circuit and architecture innovations to address these challenges. Starting from simple phase-locking concepts such as PLL, DLL and ILO, this talk will explain how the combination of these techniques is adopted in modern communication systems.
It will also describe two example cases:
i. A 28 GHz frequency synthesizer for 5G LO based beam forming, and
ii. A flexible clocking solution for 10Gb/s to 112 Gb/s SerDes in 7 nm finFET technology.
Speaker(s): , Prof. Masum Hossain
Bldg: Hub 350, 350 Legget Dr, Kanata, Ontario, Canada, K2K 0G7
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